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? semiconductor components industries, llc, 2002 january, 2002 rev. 5 1 publication order number: mc33502/d mc33502 1.0 v, rail-to-rail, dual operational amplifier the mc33502 operational amplifier provides railtorail operation on both the input and output. the output can swing within 50 mv of each rail. this railtorail operation enables the user to make full use of the entire supply voltage range available. it is designed to work at very low supply voltages (1.0 v and ground), yet can operate with a supply of up to 7.0 v and ground. output current boosting techniques provide high output current capability while keeping the drain current of the amplifier to a minimum. ? low voltage, single supply operation (1.0 v and ground to 7.0 v and ground) ? high input impedance: typically 40 fa input current ? typical unity gain bandwidth @ 5.0 v = 5.0 mhz, @ 1.0 v = 4.0 mhz ? high output current (i sc = 40 ma @ 5.0 v, 13 ma @ 1.0 v) ? output voltage swings within 50 mv of both rails @ 1.0 v ? input voltage range includes both supply rails ? high voltage gain: 100 db typical @ 1.0 v ? no phase reversal on the output for overdriven input signals ? input offset trimmed to 0.5 mv typical ? low supply current (i d = 1.2 ma/per amplifier, typical) ? 600 w drive capability ? extended operating temperature range (40 to 105 c) applications ? single cell nicd/ni mh powered systems ? interface to dsp ? portable communication devices ? low voltage active filters ? telephone circuits ? instrumentation amplifiers ? audio applications ? power supply monitor and control ? compatible with vcx logic http://onsemi.com pdip8 p suffix case 626 1 8 so8 d suffix case 751 8 mc33502p awl yyww 1 8 alyw 33502 1 8 marking diagrams 1 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc33502p pdip8 50 units/rail mc33502d so8 98 units/rail mc33502dr2 so8 2500 tape & reel pin connections 18 7 6 5 2 3 4 inputs 1 output 1 v ee v cc output 2 inputs 2 (dual, top view) 2 1
mc33502 http://onsemi.com 2 figure 1. simplified block diagram this device contains 98 active transistors per amplifier. inputs input stage outputs buffer with 0 v level shift saturation detector offset voltage trim base current boost base current boost output stage maximum ratings rating symbol value unit supply voltage (v cc to v ee ) v s 7.0 v esd protection voltage at any pin v esd 2000 v s o ec o o age a a y human body model esd 000 voltage at any device pin v dp v s 0.3 v input differential voltage range v idr v cc to v ee v common mode input voltage range v cm v cc to v ee v output short circuit duration t s note 1 s maximum junction temperature t j 150 c storage temperature range t stg 65 to 150 c maximum power dissipation p d note 1 mw 1. power dissipation must be considered to ensure maximum junction temperature (t j ) is not exceeded. 2. esd data available upon request.
mc33502 http://onsemi.com 3 dc electrical characteristics (v cc = 5.0 v, v ee = 0 v, v cm = v o = v cc /2, r l to v cc /2, t a = 25 c, unless otherwise noted.) characteristic symbol min typ max unit input offset voltage (v cm = 0 to v cc ) v io mv v cc = 1.0 v t a = 25 c 5.0 0.5 5.0 t a = 40 to 105 c 7.0 7.0 v cc = 3.0 v t a = 25 c 5.0 0.5 5.0 t a = 40 to 105 c 7.0 7.0 v cc = 5.0 v t a = 25 c 5.0 0.5 5.0 t a = 40 to 105 c 7.0 7.0 input offset voltage temperature coefficient (r s = 50 w ) d v io / d t 8.0 m v/ c t a = 40 to 105 c input bias current (v cc = 1.0 to 5.0 v) i i ib i 0.00004 10 na common mode input voltage range v icr v ee v cc v large signal voltage gain a vol kv/v v cc = 1.0 v (t a = 25 c) r l = 10 k w 25 100 r l = 1.0 k w 5.0 50 v cc = 3.0 v (t a = 25 c) r l = 10 k w 50 500 r l = 1.0 k w 25 100 v cc = 5.0 v (t a = 25 c) r l = 10 k w 50 500 r l = 1.0 k w 25 200 output voltage swing, high (v id = 0.2 v) v oh v v cc = 1.0 v (t a = 25 c) r l = 10 k w 0.9 0.95 r l = 600 w 0.85 0.88 v cc = 1.0 v (t a = 40 to 105 c) r l = 10 k w 0.85 r l = 600 w 0.8 v cc = 3.0 v (t a = 25 c) r l = 10 k w 2.9 2.93 r l = 600 w 2.8 2.84 v cc = 3.0 v (t a = 40 to 105 c) r l = 10 k w 2.85 r l = 600 w 2.75 v cc = 5.0 v (t a = 25 c) r l = 10 k w 4.9 4.92 r l = 600 w 4.75 4.81 v cc = 5.0 v (t a = 40 to 105 c) r l = 10 k w 4.85 r l = 600 w 4.7
mc33502 http://onsemi.com 4 dc electrical characteristics (continued) (v cc = 5.0 v, v ee = 0 v, v cm = v o = v cc /2, r l to v cc /2, t a = 25 c, unless otherwise noted.) characteristic unit max typ min symbol output voltage swing, low (v id = 0.2 v) v ol v v cc = 1.0 v (t a = 25 c) r l = 10 k w 0.05 0.02 r l = 600 w 0.1 0.05 v cc = 1.0 v (t a = 40 to 105 c) r l = 10 k w 0.1 r l = 600 w 0.15 v cc = 3.0 v (t a = 25 c) r l = 10 k w 0.05 0.02 r l = 600 w 0.1 0.08 v cc = 3.0 v (t a = 40 to 105 c) r l = 10 k w 0.1 r l = 600 w 0.15 v cc = 5.0 v (t a = 25 c) r l = 10 k w 0.05 0.02 r l = 600 w 0.15 0.1 v cc = 5.0 v (t a = 40 to 105 c) r l = 10 k w 0.1 r l = 600 w 0.2 common mode rejection (v in = 0 to 5.0 v) cmr 60 75 db power supply rejection psr 60 75 db v cc /v ee = 5.0 v/ground to 3.0 v/ground output short circuit current (v in diff = 1.0 v) i sc ma v cc = 1.0 v source 6.0 13 26 sink 10 13 26 v cc = 3.0 v source 15 32 60 sink 40 64 140 v cc = 5.0 v source 20 40 140 sink 40 70 140 power supply current (per amplifier, v o = 0 v) i d ma v cc = 1.0 v 1.2 1.75 v cc = 3.0 v 1.5 2.0 v cc = 5.0 v 1.65 2.25 v cc = 1.0 v (t a = 40 to 105 c) 2.0 v cc = 3.0 v (t a = 40 to 105 c) 2.25 v cc = 5.0 v (t a = 40 to 105 c) 2.5
mc33502 http://onsemi.com 5 ac electrical characteristics (v cc = 5.0 v, v ee = 0 v, v cm = v o = v cc /2, t a = 25 c, unless otherwise noted.) characteristic symbol min typ max unit slew rate (v s = 2.5 v, v o = 2.0 to 2.0 v, r l = 2.0 k w , a v = 1.0) sr v/ m s positive slope 2.0 3.0 6.0 negative slope 2.0 3.0 6.0 gain bandwidth product (f = 100 khz) gbw mhz v cc = 0.5 v, v ee = 0.5 v 3.0 4.0 6.0 v cc = 1.5 v, v ee = 1.5 v 3.5 4.5 7.0 v cc = 2.5 v, v ee = 2.5 v 4.0 5.0 8.0 gain margin (r l =10 k w , c l = 0 pf) am 6.5 db phase margin (r l = 10 k w , c l = 0 pf) f m 60 deg channel separation (f = 1.0 hz to 20 khz, r l = 600 w ) cs 120 db power bandwidth (v o = 4.0 v pp , r l = 1.0 k w , thd 1.0%) bw p 200 khz total harmonic distortion (v o = 4.5 v pp , r l = 600 w , a v = 1.0) thd % f = 1.0 khz 0.004 f = 10 khz 0.01 differential input resistance (v cm = 0 v) r in >1.0 terra w differential input capacitance (v cm = 0 v) c in 2.0 pf equivalent input noise voltage (v cc = 1.0 v, v cm = 0 v, v ee = gnd, e n nv/ hz r s = 100 w ) f = 1.0 khz 30 figure 2. representative block diagram offset voltage trim output voltage saturation detector body bias clamp v cc v cc v cc v cc in- out in+
mc33502 http://onsemi.com 6 general information the mc33502 dual operational amplifier is unique in its ability to provide 1.0 v railtorail performance on both the input and output by using a smartmos process. the amplifier output swings within 50 mv of both rails and is able to provide 50 ma of output drive current with a 5.0 v supply, and 10 ma with a 1.0 v supply. a 5.0 mhz bandwidth and a slew rate of 3.0 v/ m s is achieved with high speed depletion mode nmos (dnmos) and vertical pnp transistors. this device is characterized over a temperature range of 40 c to 105 c. circuit information input stage one volt railtorail performance is achieved in the mc33502 at the input by using a single pair of depletion mode nmos devices (dnmos) to form a differential amplifier with a very low input current of 40 fa. the normal input common mode range of a dnmos device, with an ion implanted negative threshold, includes ground and relies on the body effect to dynamically shift the threshold to a positive value as the gates are moved from ground towards the positive supply. because the device is manufactured in a pwell process, the body effect coefficient is sufficiently large to ensure that the input stage will remain substantially saturated when the inputs are at the positive rail. this also applies at very low supply voltages. the 1.0 v railtorail input stage consists of a dnmos differential amplifier, a folded cascode, and a low voltage balanced mirror. the low voltage cascoded balanced mirror provides high 1st stage gain and base current cancellation without sacrificing signal integrity. also, the input offset voltage is trimmed to less than 1.0 mv because of the limited available supply voltage. the body voltage of the input dnmos differential pair is internally trimmed to minimize the input offset voltage. a common m ode feedback path is also employed to enable the offset voltage to track over the input common mode voltage. the total operational amplifier quiescent current drop is 1.3 ma/amp. output stage an additional feature of this device is an aon demando base current cancellation amplifier. this feature provides base drive to the output power devices by making use of a buffer amplifier to perform a voltagetocurrent conversion. this is done in direct proportion to the load conditions. this aon demando feature allows these amplifiers to consume only a few microamps of current when the output stage is in its quiescent mode. yet it provides high output current when required by the load. the railtorail output stage current boost circuit provides 50 ma of output current with a 5.0 v supply (for a 1.0 v supply output stage will do 10 ma) enabling the operational amplifier to drive a 600 w load. a buffer is necessary to isolate the load current effects in the output stage from the input stage. because of the low voltage conditions, a dnmos follower is used to provide an essentially zero voltage level shift. this buffer isolates any load current changes on the output stage from loading the input stage. a high speed vertical pnp transistor provides excellent frequency performance while sourcing current. the operational amplifier is also internally compensated to provide a phase margin of 60 degrees. it has a unity gain of 5.0 mhz with a 5.0 v supply and 4.0 mhz with a 1.0 v supply. low voltage operation the mc33502 will operate at supply voltages from 0.9 to 7.0 v and ground. when using the mc33502 at supply voltages of less than 1.2 v, input offset voltage may increase slightly as the input signal swings within approximately 50 mv of the positive supply rail. this ef fect occurs only for supply voltages below 1.2 v, due to the input depletion mode mosfets starting to transition between the saturated to linear region, and should be considered when designing high side dc sensing applications operating at the positive supply rail. since the device is railtorail on both input and output, high dynamic range single battery cell applications are now possible.
mc33502 http://onsemi.com 7 20 mv/div 1.0 100 0 1000 100 0 t, time (1.0 m s/div) f, frequency (hz) t, time (500 m s/div) t a , ambient temperature ( c) figure 3. output saturation versus load resistance r l , load resistance ( w ) v cc = 2.5 v v ee = -2.5 v r l = 10 k v cc = 0.5 v v ee = -0.5 v a cl = 1.0 c l = 10 pf r l = 10 k t a = 25 c v cc = 2.5 v v ee = -2.5 v a cl = 1.0 c l = 10 pf r l = 600 w t a = 25 c v cc phase gain phase margin = 60 f m , excess phase (degrees) 0 80 60 45 40 90 180 135 20 0 100 200 10 400 1.0 600 0.1 600 0.01 400 0.001 200 0 1.0 k 10 25 10 k 100 50 100 k 1.0 k 75 1.0 m 10 k 100 10 m 100 k 1.0 m 10 m 125 v ee v cc = 5.0 v v ee = 0 v r l to v cc /2 figure 4. drive output source/sink saturation voltage versus load current source saturation t a = -55 c i o , output current (ma) v cc v ee t a = 25 c t a = 125 c sink saturation t a = 125 c t a = 25 c t a = -55 c v cc - v ee = 5.0 v 0 -0.5 -1.0 1.0 0.5 0 8.0 0 4.0 12 16 20 24 figure 5. input current versus temperature figure 6. gain and phase versus frequency figure 7. transient response figure 8. slew rate v sat, output saturation voltage (mv) v sat, output saturation voltage (v) a vol , gain (db) i ib , input current (pa) 1.0 v/div (mv)
mc33502 http://onsemi.com 8 f, frequency (hz) 100 0 1.0 2.0 3.0 8.0 4.0 5.0 1.0 k 10 k 100 k 1.0 m v cc = 2.5 v v ee = -2.5 v a v = 1.0 r l = 600 w t a = 25 c 10 6.0 7.0 -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) figure 9. maximum power dissipation versus temperature 0 200 400 600 800 1000 1200 1400 1600 dip pkg so-8 pkg figure 10. open loop voltage gain versus temperature f, frequency (hz) 100 1.0 k 10 k 100 k 10 20 60 80 120 40 100 0 0 0.5 1.0 1.5 2.0 2.5 0 20 40 60 80 100 source sink |v s | - |v o | (v) f, frequency (hz) 100 1.0 k 10 k 10 100 k psr, power supply rejection (db) 1.0 m v cc = 2.5 v v ee = -2.5 v t a = 25 c cmr, common mode rejection (db) -55 -25 50 75 100 125 t a , ambient temperature ( c) 025 120 110 100 90 80 70 60 50 40 30 20 d a vol , open loop gain (db) v cc = 2.5 v v ee = -2.5 v r l = 600 w v cc = 2.5 v v ee = -2.5 v t a = 25 c figure 11. output voltage versus frequency figure 12. common mode rejection versus frequency figure 13. power supply rejection versus frequency figure 14. output short circuit current versus output voltage 0 40 60 100 20 80 120 140 either v cc or v ee t a = 25 c v cc = 0.5 v v ee = -0.5 v v cc = 2.5 v v ee = -2.5 v v o , output voltage (v pp ) ii sc i, output short circuit current (ma) pd max, maximum power dissipation (mw)
mc33502 http://onsemi.com 9 40 percentage of amplifiers (%) input offset voltage (mv) 0 10 20 30 40 50 -5.0 v cc = 3.0 v v o = 1.5 v v ee = 0 v t a = 25 c 60 amplifiers tested from 2 wafer lots -4.0 -3.0 -2.0 -1.0 0 1.0 2.0 3.0 4.0 5.0 i cc, supply current per amplifier (ma) tc vio , input offset voltage temperature coefficient ( m v/ c) 0 10 20 30 50 -50 v cc = 3.0 v v o = 1.5 v v ee = 0 v 60 amplifiers tested from 2 wafer lots -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) 100 0 figure 15. output short circuit current versus temperature 20 40 60 80 sink source v cc = 2.5 v v ee = -2.5 v v cc , |v ee |, supply voltage (v) 2.5 0 0.5 1.0 0 0.5 1.0 1.5 figure 16. supply current per amplifier versus supply voltage with no load 1.5 2.0 2.0 2.5 t a = 125 c 100 k f, frequency (hz) 0.001 0.01 100 1.0 k 10 k 10 10 0.1 1.0 a v = 1000 v cc - v ee = 1.0 v t a = 25 c t a = -55 c -40 -30 -20 -10 0 10 20 30 40 50 a v = 100 a v = 10 a v = 1.0 100 k f, frequency (hz) 0.001 0.01 100 1.0 k 10 k 10 10 0.1 1.0 a v = 1000 v cc - v ee = 5.0 v a v = 100 a v = 10 a v = 1.0 figure 17. input offset voltage temperature coefficient distribution figure 18. input offset voltage distribution figure 19. total harmonic distortion versus frequency with 1.0 v supply figure 20. total harmonic distortion versus frequency with 5.0 v supply v out = 0.5 v pp r l = 600 w v out = 4.0 v pp r l = 600 w ii sc i, output short circuit current (ma) percentage of amplifiers (%) thd, total harmonic distortion (%) thd, total harmonic distortion (%)
mc33502 http://onsemi.com 10 0 1.0 2.0 3.0 4.0 5.0 -25 0 25 50 75 100 125 t a , ambient temperature ( c) -55 0 20 40 60 -20 -40 1.0 m 10 m f, frequency (hz) 10 k 100 k figure 21. slew rate versus temperature -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) 0 1.0 2.0 3.0 4.0 v cc - v ee = 5.0 v + slew rate -25 0 25 50 75 100 125 -55 0 20 40 0 20 40 60 80 100 60 80 100 v cc - v ee = 5.0 v r l = 600 w c l = 100 pf 10 1.0 k 1.0 m 100 100 k 10 k 0 20 40 60 70 r t , differential source resistance ( w ) phase margin gain margin c l , capacitive load (pf) 3.0 10 100 1000 3000 30 300 0 10 20 50 60 30 40 v cc - v ee = 1.0 v + slew rate v cc - v ee = 1.0 v - slew rate v cc - v ee = 5.0 v - slew rate sr, slew rate (v/ s) m v cc - v ee = 5.0 v f = 100 khz gbw, gain bandwidth product (mhz) v cc - v ee = 1.0 v v cc - v ee = 5.0 v v cc - v ee = 5.0 v v cc - v ee = 1.0 v r l = 600 w c l = 0 t a = 25 c 0 20 40 60 70 phase margin gain margin t a , ambient temperature ( c) a v , gain margin (db) v cc - v ee = 5.0 v r l = 600 w c l = 100 pf t a = 25 c 0 10 20 50 60 30 40 a v , gain margin (db) figure 22. gain bandwidth product versus temperature figure 23. voltage gain and phase versus frequency figure 24. gain and phase margin versus temperature figure 25. gain and phase margin versus differential source resistance figure 26. feedback loop gain and phase versus capacitive load v cc - v ee = 5.0 v r l = 600 w t a = 25 c 50 30 10 phase margin gain margin 10 30 50 a vol , gain (db) f m, phase margin ( ) f m, phase margin ( ) f m, phase margin ( ) a v gain margin (db)
mc33502 http://onsemi.com 11 f m, phase margin ( ) 1234567 v cc - v ee , supply voltage (v) 0 0 20 40 20 40 60 80 100 60 80 100 phase margin gain margin r l = 600 w c l = 0 t a = 25 c 10 1.0 k 100 100 k 10 20 30 40 50 60 70 10 k f, frequency (hz) v cc - v ee = 5.0 v t a = 25 c -55 -25 0 25 50 75 100 125 0 0.4 0.8 1.2 1.6 a vol 10 db r l = 600 w v cc - v ee , supply voltage (v) 0 1.0 2.0 3.0 4.0 0 20 40 60 120 5.0 6.0 r l = 600 w t a = 25 c 80 100 v cc , |v ee |, supply voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 2.0 4.0 6.0 8.0 r l = 600 w t a = 25 c figure 27. channel separation versus frequency 30 100 10 k 100 k 300 k 300 30 k a v = 100 0 20 40 100 120 60 80 v cc - v ee = 5.0 v r l = 600 w v o = 4.0 v pp t a = 25 c f, frequency (hz) a v = 10 cs, channel separation (db) 0 en, equivalent input noise voltage (nv/ hz) 0 t a , ambient temperature ( c) figure 28. output voltage swing versus supply voltage figure 29. equivalent input noise voltage versus frequency figure 30. gain and phase margin versus supply voltage figure 31. useable supply voltage versus temperature figure 32. open loop gain versus supply voltage v o , output voltage (v pp ) v cc -v ee , useable supply voltage (v) a vol, open loop gain (db) a v , gain margin (db)
mc33502 http://onsemi.com 12 r t 470 k r 2 470 k r 1b 470 k r 1a 470 k c t 1.0 nf 1.0 v f o 1.0 khz 1.0 v pp r 1 10 k r f 100 k r 2 10 k c f 400 pf 0.5 v 0.5 v c 1 80 nf v o a f f l figure 33. 1.0 v oscillator figure 34. 1.0 v voiceband filter f l 1 2 r 1 c 1 200 hz f h 1 2 r f c f 4.0 khz a f 1 r f r 2 11 + - + - f h f o 1 2r t c t in 2(r 1a r 1b ) r 2
mc33502 http://onsemi.com 13 15 v 10 79 mc34025 5 15 13 output a output b 22 k 470 pf 100 k 1.0 k from current sense 3320 1.0 k mc33502 provides current sense amplification and eliminates leading edge spike. fb 4.7 4.7 0.1 figure 35. power supply application i o d i o / d i l figure 36. 1.0 v current pump + - 12 8 14 11 4 16 6 1 3 2 i l 435 ma 463 m a 212 ma 492 m a 120 x 10 6 5.0 v v ref r 2 3.3 k r 3 1.0 k r 1 1.0 k i o 1.0 v r 4 2.4 k v l v o for best performance, use low tolerance resistors. i l + - r sense r 5 1.0 k r l 75
mc33502 http://onsemi.com 14 package dimensions notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 pdip8 p suffix case 62605 issue l
mc33502 http://onsemi.com 15 package dimensions so8 d suffix case 75107 issue w seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m
mc33502 http://onsemi.com 16 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc33502/d smartmos is a trademark of motorola, inc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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